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NCP5252 2.0 A, 1.0 MHz Integrated Synchronous Buck Regulator with Light Load Efficiency
NCP5252 is a synchronous buck regulator with integrated high-side and low-side MOSFETs. The device is capable of operating from a 5 V or 12 V supply and can output a voltage down to 0.6 V. The switching frequency is adjustable from 333 kHz up to 1.0 MHz and has the ability to provide skip mode for light load efficiency. NCP5252 protection features include Under Voltage Lock Out (UVLO), Over Voltage Protection (OVP), Cycle-by-Cycle Current Protection (OCP) and Thermal Shutdown. The parts are packaged in a 3x3mm QFN-16.
Features http://onsemi.com MARKING DIAGRAM
16 1 QFN16 CASE 485G 1 N5252 ALYWG G
COMP
FB
Typical Applications
* * * * * *
Desktop Application System Power XDSL, Modems, DC-DC Modules Set Top Box HD Driver LED Driver, DVD Recorders
QFN16 (Top View)
ORDERING INFORMATION
Device NCP5252MNTXG Package Shipping QFN16 3000 / Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2010
January, 2010 - Rev. 0
1
Publication Order Number: NCP5252/D
AGND
VO
* * * * * * * * * * * * * * * *
1% Accuracy 0.6 V Reference VCC Voltage 4.5 V to 13.2 V Adjustable Output Voltage Range: 0.6 V to 5.0 V Vout Transient Response Enhancement (TRE) Feature. Lossless Low Side Sense Current Control Input Voltage Feed Forward Control Internal Digital Soft-Start Integrated Output Discharge (Soft-Stop) Cycle-by-Cycle Current Limit PGOOD Indication Overvoltage and Undervoltage Protection Thermal Shutdown Protection Power Saving Mode at Light Load Integrated Boost Diode QFN-16 (3 mm x 3 mm) These Devices are Pb-Free and are RoHS Compliant
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
16 VCC BST PGOOD EN/SKIP 1 2 3 4 5
15
14
PGND 13 12 11 10 9 PGND PGND V5 FREQ_SET 8
VCC
LX 6
NCP5252
LX 7
NCP5252
V5
Thermal Shutdown
LDO UVLO Control OC monitor
VCC
EN / SKIP
Level Control
ENABLE FPWM SKIP
BST
PGOOD
PGOOD VREF+10% + PGH - + VREF-15% VREF-20% - + - - VREF + VREF+15% + - OVP UVP PGL Control Logic, Protection, RAMP Generator and PWM Logic Soft stop NCP5252 LX VO
OC monitor
FB
VCC
COMP
Error Amplifier OSC / DIV
FREQ_SET PGND
AGND
Figure 1. NCP5252 Typical Block Diagram
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NCP5252
4.5 TO 13.2V
EN / SKIP
PGOOD
BST
vcc
COMP FB NCP5252 VO FREQSET AGND
LX VOUT
PGND
V5
GND
Figure 2. NCP5252 Typical Application Circuits
PIN FUNCTION DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11-13 14-15 16 17 Symbol VCC BST PGOOD EN/SKIP COMP FB VO AGND FREQ_SET V5 PGND LX VCC EPAD Internal LDO power supply Top MOSFET driver input supply, a bootstrap capacitor connection between LX and this pin. Power good indicator of the output voltage. High impedance (open drain) if power good (in regulation). Low impedance if power not good. This pin serves as two functions. Enable: Logic control for enabling the switcher. SKIP: Power saving mode (Skip and Force PWM) programmable pin. Output of the error amplifier. Output voltage feed back. Output voltage. Analog ground. Frequency selection pin, 0 V = 333k, No connect = 500 kHz, 5 V = 1.0 MHz Power supply for analog circuit. Ground reference and high-current return path for the bottom power MOSFET. Switch node between the top MOSFET and bottom MOSFET. Internal Main FET power supply Connect to PGND for thermal enhancement. Exposed pad is not electrically connected.
Description
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NCP5252
ABSOLUTE MAXIMUM RATINGS
Rating VCC Power Supply Voltage to AGND EN / SKIP to AGND Bootstrap Supply Voltage: BST to LX LDO regulator: V5 to AGND Input / Output Pins to AGND Switch Node to PGND Symbol VCC VEN VBST - VLX V5 - VAGND VIO VLX Value -0.3, 15 -0.3, 15 -0.3, 15 -0.3, 6 -0.3, 6 15 -1 (DC) -5 (200 ns) -0.3, 0.3 90 15 -40 to + 85 -40 to + 150 -55 to +150 1.4 1 Unit V V V V V V
PGND Thermal Resistance Junction-to-Ambient (0 lfpm) Thermal Resistance Junction-to-Case (0 lfpm) Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Power Dissipation Moisture Sensitivity Level
VPGND RqJA RqJC TA TJ Tstg PD MSL
V C/W C/W C C C W -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
VCC UNDERVOLTAGE
Parameter VCC UVLO Rise Threshold VCC UVLO Hysteresis Test Conditions Min 4.1 300 Typ 4.3 400 Max 4.5 500 Unit V mV
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NCP5252
ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 13.2 V, TA = -40C to 85C, unless other noted)
Characteristics SUPPLY VOLTAGE Input Voltage POR Threshold for Internal Reset Logic SUPPLY CURRENT VCC Quiescent Supply Current VCC Shutdown Current BST Quiescent Supply Current BST Shut Down Current VCC Input Current LDO REGULATOR V5 Regulator Voltage V5 Rise Threshold V5 UVLO Hysteresis V5 Loading V5 Current Limit Drop-out Voltage (VCC - V5) POWER GOOD Power Good High Threshold Power Good High Hysteresis Power Good Low Threshold Power Good Low Hysteresis Power Good High Delay Power Good Low Delay Output Overvoltage Rising Threshold Over voltage Fault Propagation Delay Output Undervoltage Trip Threshold Output Undervoltage Protection Blanking Time REFERENCE OUTPUT Internal Reference Voltage Output Voltage Accuracy (Note 1) Line Regulation (Note 1) OSCILLATOR Operation Frequency FSW FREQ_SET = V5 FREQ_SET = NC FREQ_SET = AGND INTERNAL SOFT-START Soft-Start Time tSS Digital Soft-Start (VOUT from 10% to 90%) 800 ms 1. Guaranteed by design, not tested in production. 2. Test mode disables the Ton/Toff min. 900 450 300 1000 500 333 1100 550 366 kHz kHz kHz VREF 25C -40C to 85C VIN = 12 V, Io = 0 A to 2 A VIN = 5 to 12 V, IOUT = 500 mA 0.594 0.591 -1 0.6 0.6 0 0.1 0.606 0.609 +1 V % %/V VPGH VPGH_HYS VPGL VPGL_HYS Td_PGH Td_PGL OVPth+ OVPTblk UVPth UVPTblk OVPth+ = VPGH + VPGH_SYS FB Forced 2% above trip threshold UVPth = VPGL + VPGL_HYS 70 105 PGOOD in from higher Vo (PGOOD goes high) PGOOD high hysteresis (PGOOD goes low) PGOOD in from lower Vo (PGOOD goes high) PGOOD low hysteresis (PGOOD goes low) 75 100 110 5 85 -5 150 1.5 115 1.5 80 8.0 90 125 95 120 % % % % ms ms % ms % ms V5 V5_th+ V5HYS V5LOAD ILIMIT_V5 VDR Io = 5 mA, TA = 25C, VCC = 4.5 V, FB = 1V 20 200 VCC > 6 V, IV5 = 5 mA Wake Up 4.85 4.1 300 5.0 4.3 400 5.15 4.45 500 3.0 V V mV mA mA mV ICC_FPWM IVCC_SD IBST_FPWM IBST_SD IVCC EN/SKIP = 5 V, VFB = 1 V (No switching), VCC = 4.5 V to 13.2 V EN/SKIP = 0 V EN/SKIP = H, VFB = 1 V, VBST = 5 V EN/SKIP = L, VFB = 1 V, VBST = 5 V FREQ_SET = AGND. FREQ = 333 kHz 18 1.0 2.5 10 0.3 10 mA mA mA mA mA VCC VCC_POR 4.5 3.0 13.2 3.7 V V Symbol Test Conditions Min Typ Max Unit
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NCP5252
ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 13.2 V, TA = -40C to 85C, unless other noted)
Characteristics SWITCHING MODULATOR Minimum Ton Minimum Toff PWM Comparator Offset Propagation Delay of PWM Comparator VOLTAGE ERROR AMPLIFIER DC Gain Open-Loop Phase Margin Unity Gain Bandwidth Slew Rate FB Bias Current Output Voltage Swing OVERCURRENT PROTECTION LIMIT High Side Peak Current Limit (Cycle-by-Cycle) Low Side Valley Current Limit, Short-Circuit (4 ms) Low Side Valley Current Limit (Current Limit, 16 ms) POWER OUTPUT SECTION Internal Main FET ON-Resistance Internal Sync FET ON-Resistance LX Leakage Current CONTROL SECTION EN / SKIP Logic Input Voltage for Disable EN / SKIP Logic Input Voltage for FPWM EN / SKIP Logic Input Voltage for Skip Mode EN / SKIP Source Current EN / SKIP Sink Current EN_SKIP Logic Input Delay PGOOD Pin ON Resistance PGOOD Pin OFF Current OUTPUT DISCHARGE MODE Output Discharge On-Resistance THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis Tsd Tsdhys (Note 1) (Note 1) 150 25 C C Rdischarge EN = 0 V 20 35 W PGOOD_R PGOOD_LK VEN_DISABLE VEN_HYS VEN_FPWM VEN_SKIP VEN_HYS IEN_SOURCE IEN_SINK Set as Disable Hysteresis Set as FCCM mode Set as SKIP Mode Hysteresis VEN_SKIP = 0 V VEN_SKIP = 5 V Change mode delay active I_PGOOD = 5 mA PGOOD = 5 V 3 75 1 1.7 2.25 0.7 1.0 300 1.95 2.45 250 0.1 0.1 2.10 2.65 1.3 V mV V V mV mA mA Clk W mA RDS(on)_M RDS(on)_F LX_LK (ILX=100mA, VBST-LX = 5 V, FB = 0, TA = 25C) (Note 1) (ILX = 100 mA, FB = 1 V, TA = 25C) (Note 1) VEN = 0V, LX = 0, VCC = 13.2 V LX = 13.2, VCC = 13.2 V 150 100 225 150 +5.0 -5.0 mW mW mA mA HSOC LSOC_S LSOC_L Ton Minimum > 100 ns (Notes 1 & 2) (Notes 1 & 2) (Notes 1 & 2) 3.4 3.0 2.0 4.0 3.75 2.5 4.6 4.5 3.4 A A A GAIN_VEA PH_EA BW_VEA SR_VEA Ibias_FB Vmax_EA Vmin_EA Isource_EA = 2mA Isink_EA = 2mA 3.3 3.5 0.15 0.3 (Note 1) (Note 1) (Note 1) COMP PIN TO GND = 100 pF (Note 1) 80 50 15 5.0 0.1 20 88 dB Deg MHz V/ms mA V V TD_PWM Ton_min Toff_min (Note 1) (Note 1) (Note 1) (Note 1) 40 200 50 225 5.0 60 250 10 20 ns ns mV ns Symbol Test Conditions Min Typ Max Unit
1. Guaranteed by design, not tested in production. 2. Test mode disables the Ton/Toff min.
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NCP5252
TYPICAL OPERATING CHARACTERISTICS
175 150 125 100 75 50 25 -50 VTHUVLO, UVLO THRESHOLD (V) 4.375 4.350 4.325 4.300 4.275 4.250 4.225 -50
RDS(on), SWITCH ON RESISTANCE (mW)
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
Figure 3. Sync FET ON Resistance vs. Temperature
1075 fOSC, SWITCHING FREQUENCY (MHz) 1050 1025 1000 975 950 925 -50 VFB, FEEDBACK VOLTAGE (mV) 603 602 601 600 599 598 597 -50
Figure 4. UVLO Threshold vs. Temperature
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
Figure 5. Switching Frequency vs. Temperature
ICC, QUIESCENT CURRENT into VCC (mA) 1.40 1.35 1.30 1.25 1.20 1.15 1.10 -50 VICC_SD, SHUTDOWN QUIESCENT CURRENT (mA) 4.75 4.50 4.25 4.00 3.75 3.50 3.25 -50
Figure 6. Feedback Input Threshold vs. Temperature
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
-25 0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
Figure 7. Quiescent Current into VCC vs. Temperature
Figure 8. Shutdown Quiescent Current vs. Temperature
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NCP5252
TYPICAL OPERATING CHARACTERISTICS
0.75 0.50 0.25 0.00 100 90 OUTPUT EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.01 VIN = 12 V, VOUT = 3.3 V, L = 5 mH, Freq = 500 kHz
DVOUT, OUTPUT VOLTAGE CHANGE (%)
-0.25 -0.50 -0.75 0.01
VIN = 12 V, VOUT = 3.3 V, L = 5 mH, Freq = 500 kHz
0.1 1 IOUT, OUTPUT CURRENT (A)
10
0.1 1 IOUT, OUTPUT CURRENT (A)
10
Figure 9. Output Voltage Change vs. Output Current
DVOUT, OUTPUT VOLTAGE CHANGE (%) 0.75 0.50 0.25 0.00 100 90 OUTPUT EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.01
Figure 10. Efficiency vs. Output Current
-0.25 -0.50 -0.75 0.01
VIN = 5 V, VOUT = 3.3 V, L = 5 mH, Freq = 500 kHz
VIN = 5 V, VOUT = 3.3 V, L = 5 mH, Freq = 500 kHz
0.1 1 IOUT, OUTPUT CURRENT (A)
10
0.1 1 IOUT, OUTPUT CURRENT (A)
10
Figure 11. Output Voltage Change vs. Output Current
DVOUT, OUTPUT VOLTAGE CHANGE (%) 0.75 0.50 0.25 0.00 100 90 OUTPUT EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.01
Figure 12. Efficiency vs. Output Current
-0.25 -0.50 -0.75 0.01
VIN = 5 V, VOUT = 1.2 V, L = 5 mH, Freq = 500 kHz
VIN = 12 V, VOUT = 1.2 V, L = 5 mH, Freq = 500 kHz
0.1 1 IOUT, OUTPUT CURRENT (A)
10
0.1 1 IOUT, OUTPUT CURRENT (A)
10
Figure 13. Output Voltage Change vs. Output Current
Figure 14. Efficiency vs. Output Current
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NCP5252
(Vin = 12 V, ILOAD = 10 mA, L = 5 mH,COUT = 100 mF) Upper trace: Input voltage, 5 V/div Lower trace: Output voltage, 1 V/div Time base: 500 ms/div
(Vin = 12 V, ILOAD = 10 mA, L = 5 mH,COUT = 100 mF) Upper trace: Input voltage, 5 V/div Lower trace: Output voltage, 1 V/div Time base: 500 ms/div
Figure 15. Soft-Start Waveforms for Vout = 3.3 V
Figure 16. Soft-Start Waveforms for Vout = 1.2 V
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NCP5252
(Vin = 12 V, ILOAD = 200 mA, L = 5 mH, COUT = 100 mF) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 1 A/div Time base: 2 ms/div
(Vin = 12 V, ILOAD = 1 A, L = 5 mH, COUT = 100 mF) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 1 A/div Time base: 2 ms/div
Figure 17. DCM Switching Waveforms for Vout = 1.2 V
Figure 18. CCM Switching Waveforms for Vout = 1.2 V
(Vin = 12 V, ILOAD = 200 mA, L = 5 mH, COUT = 100 mF) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 500 mA/div Time base: 2 ms/div
(Vin = 12 V, ILOAD = 500 mA, L = 5 mH, COUT = 100 mF) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 500 mA/div Time base: 2 ms/div
Figure 19. DCM Switching Waveforms for Vout = 3.3 V
Figure 20. CCM Switching Waveforms for Vout = 3.3 V
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NCP5252
(Vin = 12 V, L = 5 mH, COUT = 100 mF, Freq = 500 kHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 ms/div
(Vin = 5 V, L = 5 mH, COUT = 100 mF, Freq = 1 MHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 ms/div
Figure 21. Load Transient Response for Vout = 1.2 V
Figure 22. Load Transient Response for Vout = 1.2 V
(Vin = 12 V, L = 5 mH, COUT = 100 mF, Freq = 1 MHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 ms/div
(Vin = 5 V, L = 5 mH, COUT = 100 mF, Freq = 333 kHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 ms/div
Figure 23. Load Transient Response for Vout = 3.3 V
Figure 24. Load Transient Response for Vout = 3.3 V
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NCP5252
DETAILED OPERATING DESCRIPTION
General
The NCP5252 is a PWM regulator intended for DC-DC conversion from 5 V & 12 V buses and supplies up to a 2 A load. The NCP5252 is a step down synchronous-rectifier buck topology regulator with integrated high-side and a low-side NMOS switch. The output voltage of the converter can be precisely regulated down to 600 mV 1.0% when the VFB pin is tied to VOUT. The switching frequency can be adjusted to 333 kHz, 500 kHz or 1 MHz. A skip mode can be enabled to provide light load efficiency. The NCP5252 includes features like power good monitor, internal soft-start, cycle-by-cycle current limit, short circuit protection, output undervoltage/overvoltage protection and thermal shutdown.
Control Logic
response enhancement circuitry is implemented inside the NCP5252. In CCM operation, the controller is continuously monitoring the COMP pin output voltage of the error amplifier and detecting the load transient events. The functional block diagram of TRE is shown as follows:
COMP R C Internal TRE_TH + TRE
Figure 25. Block Diagram of TRE Circuit
The internal control logic is powered by an internal LDO. The device is controlled by EN/SKIP pin. The EN/SKIP serves two functions. When voltage of EN/SKIP is below VEN_DISABLE, the converter will shut down. If the voltage of EN/SKIP is set between VEN_FPWM and VEN_SKIP, the device will force to PWM mode operation. When voltage level of EN/SKIP is above VEN_SKIP, the device will operate in PFM power saving mode. During start-up, the internal LDO is activated and power-on reset occurs which resets the logic and all protection faults. Once VREF reaches its regulation voltage, an internal signal will wake up the supply undervoltage monitor which will assert a "GOOD" condition. In addition, the NCP5252 continuously monitors VCC level with an undervoltage lockout (UVLO) function.
Forced PWM Operation (FPWM Mode)
Once the large transient occurs, the COMP signal may be large enough to exceed the threshold and then TRE "flag" signal will be asserted in a short period which is typically around one normal switching cycle. In this short period, the controller will be running at high frequency and hence has faster response. After that the controller comes back to normal switching frequency operation.
Overcurrent Protection (OCP)
The device is operating in the force PWM mode if an EN/SKIP pin voltage is set between VEN_FPWM and VEN_SKIP threshold. The low-side Power MOSFET is forced to be the complement of high-side Power MOSFET. This allows reverse inductor current. During the soft-start operation, the NCP5252 will automatically run as FPWM mode until output voltage is higher than internal soft-start ramp.
Pulse Skipping Operation (Skip Mode/PFM)
The NCP5252 will protect the system if an overcurrent event occurs. The regulator will continuously monitor the output current through the internal MOSFETs. If the main MOSFET current exceeds the internal current limit threshold, it will be turned off. If a repetitive overcurrent event occurs, both MOSFETs will be turned off and the device will hold for 3 normal soft-start periods before re-starting. A discharge resistor is turned on to discharge Vo before re-starting.
Overvoltage Protection (OVP)
When the SMPS output voltage is above 115% (typ) of the preset nominal regulation voltage for over 1.5 ms, an OV fault is set. The high side MOSFET will turn off and the bottom side MOSFET will be turned on to discharge the output until Vo drops below the default threshold (105%). Then the device will recover to normal regulation.
Undervoltage Protection (UVP)
The device operates as skip mode if EN/SKIP pin voltage is higher than 2.9 V. Skip mode can reduce the switching loss at light load condition. When the converter inductor current is higher than zero, the converter will run in continuous-conduction-mode (CCM) which behaves exactly the same as FPWM mode. In a light load condition, the regulator will automatically transition to skip mode.
Transient Response Enhancement (TRE)
A UVP circuit monitors the output voltage to detect an undervoltage event. The undervoltage limit is 80% (typ) of the nominal output voltage level. If the output voltage is below this threshold for over 4 clock cycles, an UVP fault is set and the device will hold for 3 soft-start periods and then restart the regulator through the soft-start cycle. Before the soft-start time, a discharge resistor is turned on to discharge Vo before re-starting.
For the conventional PWM controller in CCM, the fastest response time is one switching cycle in the worst case. To further improve transient response in CCM, a transient
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NCP5252
LDO Regulator
The internal LDO regulator (V5) can provide up to 20 mA typically for internal use. Connect a capacitor to pin V5 for proper regulation.
Undervoltage Logout
When the VCC voltage is higher than 4.0 V, the UVLO flag will be cleared and the soft-start function will activate.
Thermal Shutdown
The UVLO circuit will activate when the VCC voltage is below 3.5 V (typ). At that time both MOSFETs will turn off.
The IC will shutdown if the die temperature exceeds 150C. The IC will restart with soft-start operation only after the junction temperature drops below 125C.
4.5 TO 13.2V
C1 EN / SKIP PGOOD BST VCC L1 LX VOUT
C2
R1 COMP FB
NCP5252 VO FREQSET AGND PGND C3 V5 C4 R4 R2
R3 GND
Figure 26. Typical Application Circuit
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NCP5252
Table 1. Typical Design Value
For Vcc = 12 V Application Vin (V) 12 12 12 12 12 12 12 12 12 Vin (V) 5 5 5 5 5 5 Vout (V) 5 3.3 1.2 5 3.3 1.2 5 3.3 1.2 Vout (V) 3.3 1.2 3.3 1.2 3.3 1.2 Fsw (kHz) Any Any Any Any Any Any Any Any Any Fsw (kHz) Any Any Any Any Any Any C1 (pF) 10 10 10 10 10 10 10 10 10 C1 (pF) 10 10 10 10 10 10 C2 (nF) 2.0 2.0 2.0 2.0 2.0 2.0 1.0 1.0 1.0 C2 (nF) 2.0 2.0 2.0 2.0 1.0 1.0 R1 (kW) 23 23 23 54 54 54 30 30 30 R1 (kW) 56 56 100 100 60 60 R2 (kW) 10 10 10 10 10 10 10 10 10 R2 (kW) 10 10 10 10 10 10 R3 (kW) 1.4 2.2 10 1.4 2.2 10 1.4 2.2 10 R3 (kW) 2.2 10 2.2 10 2.2 10 R4 (W) 200 200 200 200 200 200 NC NC NC R4 (W) 200 200 200 200 NC NC C3 (pF) 800 800 800 800 800 800 NC NC NC C3 (pF) 800 800 800 800 NC NC C4 (mF) Ceramic 22 mF x 2 Ceramic 22 mF x 2 Ceramic 22 mF x 2 SP 100 mF / 12 mW SP 100 mF / 12 mW SP 100 mF / 12 mW Electrolytic 470 mF/160 mW Electrolytic 470 mF/160 mW Electrolytic 470 mF/160 mW C4 (mF) Ceramic 22 mF x 2, ESR = 4 mW Ceramic 22 mF x 2, ESR = 4 mW SP 100 mF / ESR = 12 mW SP 100 mF / ESR = 12 mW Electrolytic 470 mF/ESR = 160 mW Electrolytic 470 mF/ESR = 160 mW L1 (mH) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 L1 (mH) 5.0 5.0 5.0 5.0 5.0 5.0
For Vcc = 5 V Application
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NCP5252
TIMING DIAGRAMS
Timing 1 (SMPS Enable and Disable by EN_SKIP)
VIN
EN_SKIP
V5 Discharged by Ridscharge + Ext. Load SMPS VOUT Discharged by Ext. Load Only
PGOOD
Logic Block Ready when VCC > PORth Device Ready when VCC > VINth
PGOOD Asserts When VOUT Within Window SMPS Soft Start Begins After Detection
Soft Stop Begins When EN_SKIP=L Note: PORth = ~2.5V
Figure 27. Timing 2 (SMPS OVP & UVP Operation)
VCC 115% SMPS VOUT 85% 80% 110% 110% 105%
SS TG
BG
Hiccup
3 soft start time
PGOOD
Outside PGOOD window
Outside PGOOD window
Soft Stop continue discharge
Inside PGOOD window
Hit OVP threshold
Inside PGOOD window
Hiccup delay
Soft start again
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NCP5252
PACKAGE DIMENSIONS
QFN16, 3x3, 0.5P CASE 485G-01 ISSUE D
D A B L L1 DETAIL A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG
PIN 1 LOCATION
0.15 C 0.15 C
TOP VIEW
A1
0.10 C
DETAIL B
(A3) A
DETAIL B
ALTERNATE CONSTRUCTIONS
16 X
0.08 C SIDE VIEW A1 C
SEATING PLANE
MOUNTING FOOTPRINT*
4.30 2.25
16X
L
DETAIL A 5 4
D2
8
e
EXPOSED PAD
NOTE 5
1
9
16X
K
1 16 16X 13
E2
12
e
4.30 2.25
b BOTTOM VIEW 0.78
16X 16X
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CC CC EE
EE EE EE
CCC CCC CCC
E
EXPOSED Cu
ALTERNATE TERMINAL CONSTRUCTIONS
MOLD CMPD
A3
DIM A A1 A3 b D D2 E E2 e K L L1
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15
PKG OUTLINE
PITCH
0.65
0.35
DIMENSIONS: MILLIMETERS
NCP5252/D

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